Datasheet
H.265 HD Decoder Codec Module
2dc-va-h265-10b-30-1080-md00c-sx660
MCM Codec Modules Overview

SOC Mpeg Codec Modules (MCMs) are small yet powerful video processing PCBs designed to reduce the engineering effort needed to make use of our low-latency all-hardware video/audio Codec IP.

MCM Modules are built with all the IC and interfaces that our Codec IP cores need to process real-time video:

  • a high-performance Xilinx/Intel FPGA/SoC
  • DDR memory
  • Flash/EEPROM
  • Audio-codec capabilites
  • Run-time API interface

MCM modules are pre-loaded with firmware according to customer specifications. They are shipped as ready to use, plug-in-and-play Codec processing systems.

To use MCM modules, add a 204-pin card connector on your PCB, and you are ready to encode/decode/transcode up to 4K/60 video (3840x2160 at 60fps), at ultra-low latencies (as low as 0.25ms!).

Product Overview
Edge-connector Card Interface

MCM Modules interface to user PCBs via a standard 204-pin SODIMM connector. You may recognize this connector as the DDR3 SDRAM connector used for connecting high-speed RAM to PCs. Coincidentally, this connector is also well-suited for streaming uncompressed and compressed video data.

You may purchase this connector from various electronics parts suppliers:

MM80 Series Inline Module Socket Connector
Manufacturer: JAE Electronics
Mouser - MM80-204B1-1
204-pin DDR3 SDRAM SODIMM Connector
Manufacturer: TE Connectivity AMP Connectors
DigiKey - 2-2013289-1
Edge Connector Signals

Working reference designs may be licensed from System-On-Chip Technologies.

Uncompressed Video Signals
HD video signals

Video data is transferred on the HDMI_D[] data bus. Vertical sync and horizontal sync signals are used for frame synchronization.

10-bit capable systems use 10 bits per channel, 8-bit systems ignore the 2 lowest bits [1:0] (they can be set to '0').

Signal NameDir.Description
HDMI_CLKIVideo Clock
HDMI_D[17:0]IHDMI Luma and Chroma Data
Video Clock

VIDEO_CLK is driven by the video source (usually HDMI or SDI chipset). VIDEO_CLK frequency should be set according to the resolution and framerate of the video source:

Resolution /FPSClock Frequency
640x480p 60fps27 Mhz
1280x720p 60fps74.25 Mhz
1920x1080p 30fps74.25 Mhz
1920x1080p 60fps148.5 Mhz
Compressed Data Stream Signals

Compressed data is transferred as an 8-bit stream over TS_BYTE[7:0] lines. At every rising edge of TS_CLK, if TS_DV is '1', this means that the current data on the TS_DATA bus is valid for reading.

Signal NameDir.Description
TS_CLKIStream Clock
TS_RDYOReceiver Ready
TS_DVIData Valid
TS_BYTE[7:0]IStream Data
UART Signals (API)

Modules expose a serial UART interface for reading/writing API registers. For a list of available API registers, refer to the API Guide.

Signal NameDir.Description
UART_RXIUART data to module
UART_TXOUART data from module

The standard UART protocol uses these parameters:

BaudrateData bitsStart bitsStop bitsParity bits
1152008110
Voltage Requirements

Working reference designs may be licensed from System-On-Chip Technologies.