Datasheet
H.264 4K Decoder Codec Module
dc-v-h264-8b-30-4k-m-ll
MCM Codec Modules Overview

SOC Mpeg Codec Modules (MCMs) are small yet powerful video processing PCBs designed to reduce the engineering effort needed to make use of our low-latency all-hardware video/audio Codec IP.

MCM Modules are built with all the IC and interfaces that our Codec IP cores need to process real-time video:

  • a high-performance Xilinx/Intel FPGA/SoC
  • DDR memory
  • Flash/EEPROM
  • Audio-codec capabilites
  • Run-time API interface

MCM modules are pre-loaded with firmware according to customer specifications. They are shipped as ready to use, plug-in-and-play Codec processing systems.

To use MCM modules, add a 204-pin card connector on your PCB, and you are ready to encode/decode/transcode up to 4K/60 video (3840x2160 at 60fps), at ultra-low latencies (as low as 0.25ms!).

Product Overview
Edge-connector Card Interface

MCM Modules interface to user PCBs via a standard 204-pin SODIMM connector. You may recognize this connector as the DDR3 SDRAM connector used for connecting high-speed RAM to PCs. Coincidentally, this connector is also well-suited for streaming uncompressed and compressed video data.

You may purchase this connector from various electronics parts suppliers:

MM80 Series Inline Module Socket Connector
Manufacturer: JAE Electronics
Mouser - MM80-204B1-1
204-pin DDR3 SDRAM SODIMM Connector
Manufacturer: TE Connectivity AMP Connectors
DigiKey - 2-2013289-1
Edge Connector Signals

Working reference designs may be licensed from System-On-Chip Technologies.

Edge PadSignalDirection
27SPDIFO
29USE_VTRBI
31TS_CLKI
33TS_DVI
38VIDEO_C[20]O
40VIDEO_C[21]O
46TS_D[0]I
48TS_D[1]I
50VIDEO_C[22]O
52VIDEO_C[23]O
54VIDEO_C[24]O
56VIDEO_C[25]O
58VIDEO_C[26]O
59VIDEO_C[28]O
60VIDEO_C[27]O
61VIDEO_C[29]O
65TS_D[3]I
67VIDEO_DEO
69TS_D[2]I
76SDI_CLKO
77VIDEO_Y[20]O
78VIDEO_Y[26]O
79VIDEO_Y[21]O
80VIDEO_FRAME_SYNC_CLOCKO
81VIDEO_Y[22]O
82VIDEO_Y[27]O
83VIDEO_Y[23]O
84VIDEO_Y[28]O
85VIDEO_Y[24]O
86VIDEO_Y[29]O
87VIDEO_Y[25]O
88UART_RXI
89VIDEO_C[10]O
90UART_TXO
91VIDEO_C[11]O
92VIDEO_Y[16]O
Edge PadSignalDirection
93VIDEO_C[12]O
94VIDEO_Y[17]O
95VIDEO_C[13]O
96VIDEO_Y[18]O
97VIDEO_C[14]O
98VIDEO_Y[19]O
99VIDEO_C[15]O
100VIDEO_Y[36]O
101VIDEO_C[16]O
102VIDEO_Y[37]O
103VIDEO_C[17]O
104VIDEO_Y[38]O
105VIDEO_CLOCK_0O
106VIDEO_Y[39]O
107VIDEO_Y[30]O
108VIDEO_C[30]O
109VIDEO_C[18]O
110VIDEO_C[31]O
111VIDEO_C[19]O
112VIDEO_C[32]O
113VIDEO_VSO
114VIDEO_C[33]O
115VIDEO_Y[32]O
116VIDEO_Y[2]O
117VIDEO_Y[10]O
118VIDEO_Y[3]O
119VIDEO_Y[11]O
120TS_BYTE[7]I
121VIDEO_Y[12]O
122VIDEO_Y[31]O
123VIDEO_Y[13]O
124VIDEO_Y[4]O
125VIDEO_Y[14]O
126VIDEO_Y[5]O
127VIDEO_Y[15]O
128VIDEO_Y[6]O
Edge PadSignalDirection
130VIDEO_Y[7]O
131FLASH_DVI
132VIDEO_Y[8]O
133VIDEO HSO
134VIDEO_Y[9]O
135VIDEO_Y[0]O
136VIDEO_C[34]O
137VIDEO_Y[1]O
138VIDEO_C[35]O
139VIDEO_C[36]O
140VIDEO_C[38]O
141VIDEO_C[37]O
142VIDEO_C[39]O
143VIDEO_C[0]O
1443G_HDO
145VIDEO_C[1]O
146VIDEO_Y[33]O
147VIDEO_C[2]O
148VIDEO_Y[34]O
149VIDEO_C[3]O
150VIDEO_Y[35]O
151VIDEO_C[4]O
152TS_BYTE[0]I
153VIDEO_C[5]O
154TS_BYTE[1]I
155VIDEO_C[6]O
156PS_SRST_BI
157VIDEO_C[7]O
158TS_BYTE[2]I
159VIDEO_C[8]O
160TS_BYTE[3]I
161VIDEO_C[9]O
162TS_BYTE[4]I
164TS_BYTE[5]I
166TS_BYTE[6]I
Uncompressed Video Signals
4K video signals

4K video is transmitted as four synchronized HD quadrants.

Video data is transferred on HDMII_D[] and VIDEO_C[] data busses. VIDEO_VS (vertical sync) and VIDEO_HS (horizontal sync) signals are used for frame synchronization.

10-bit capable systems use 10 bits per channel, 8-bit systems ignore the 2 lowest bits [1:0] (they can be set to '0').

Signal NameDir.Description
VIDEO_HSIHorizontal-Sync
VIDEO_VSIVertical-Sync
VIDEO_CLK_0IQuadrant-0 (top-left, primary) Video Clock
VIDEO_Y[9:0]IQ-0 Luma
VIDEO_C[9:0]IQ-0 Chroma
VIDEO_CLK_1IQuadrant-1 (top-right) Video Clock
VIDEO_Y[19:10]IQ-1 Luma
VIDEO_C[19:10]IQ-1 Chroma
VIDEO_CLK_2IQuadrant-2 (bottom-left) Video Clock
VIDEO_Y[29:20]IQ-2 Luma
VIDEO_C[29:20]IQ-2 Chroma
VIDEO_CLK_3IQuadrant-3 (bottom-right) Video Clock
VIDEO_Y[39:30]IQ-4 Luma
VIDEO_C[39:30]IQ-4 Chroma
Video Clock

VIDEO_CLK is driven by the video source (usually HDMI or SDI chipset). VIDEO_CLK frequency should be set according to the resolution and framerate of the video source:

Resolution /FPSClock Frequency
640x480p 60fps27 Mhz
1280x720p 60fps74.25 Mhz
1920x1080p 30fps74.25 Mhz
1920x1080p 60fps148.5 Mhz
Compressed Data Stream Signals

Compressed data is transferred as an 8-bit stream over TS_BYTE[7:0] lines. At every rising edge of TS_CLK, if TS_DV is '1', this means that the current data on the TS_DATA bus is valid for reading.

Signal NameDir.Description
TS_CLKIStream Clock
TS_RDYOReceiver Ready
TS_DVIData Valid
TS_BYTE[7:0]IStream Data
UART Signals (API)

Modules expose a serial UART interface for reading/writing API registers. For a list of available API registers, refer to the API Guide.

Signal NameDir.Description
UART_RXIUART data to module
UART_TXOUART data from module

The standard UART protocol uses these parameters:

BaudrateData bitsStart bitsStop bitsParity bits
1152008110
Voltage Requirements

Working reference designs may be licensed from System-On-Chip Technologies.

Edge PadVoltage
1VCC_3V3
2GND
3VCC_3V3
4GND
5VCC_3V3
6GND
7VCC_3V3
8GND
9VCC_3V3
10VCC_1V2
11VCC_3V3
12VCC_1V2
13VCC_3V3
14VCC_1V2
15VCC_3V3
16VCC_1V2
17GND
18GND
19NC
20GND
21NC
22VCC_1V5
23NC
24VCC_1V5
25NC
26VCC_1V5
27IO_1V5
28VCC_1V5
29IO_1V5
30VCC_1V5
31IO_1V5
32VCC_1V5
33IO_1V5
34GND
Edge PadVoltage
35GND
36GND
37GND
38IO_3V3
39GND
40IO_3V3
41GND
42GND
43VCCINT_1V0
44GND
45VCCINT_1V0
46IO_1V5
47VCCINT_1V0
48IO_1V5
49VCCINT_1V0
50IO_3V3
51VCCINT_1V0
52IO_3V3
53VCCINT_1V0
54IO_3V3
55VCCINT_1V0
56IO_3V3
57VCCINT_1V0
58IO_3V3
59IO_3V3
60IO_3V3
61IO_3V3
62GND
63IO_1V5
64JTAG_TDI
65IO_1V5
66JTAG_TMS
67IO_1V5
68JTAG_TDO
Edge PadVoltage
69IO_1V5
70JTAG_TCK
71GND
72GND
73GND
74GND
75GND
76IO_3V3
77IO_3V3
78IO_3V3
79IO_3V3
80IO_3V3
81IO_3V3
82IO_3V3
83IO_3V3
84IO_3V3
85IO_3V3
86IO_3V3
87IO_3V3
88IO_3V3
89IO_3V3
90IO_3V3
91IO_3V3
92IO_3V3
93IO_3V3
94IO_3V3
95IO_3V3
96IO_3V3
97IO_3V3
98IO_3V3
99IO_3V3
100IO_3V3
101IO_3V3
102IO_3V3
Edge PadVoltage
103IO_3V3
104IO_3V3
105IO_3V3
106IO_3V3
107IO_3V3
108IO_3V3
109IO_3V3
110IO_3V3
111IO_3V3
112IO_3V3
113IO_3V3
114IO_3V3
115IO_3V3
116IO_1V5
117IO_3V3
118IO_1V5
119IO_3V3
120IO_3V3
121IO_3V3
122IO_3V3
123IO_3V3
124IO_1V5
125IO_3V3
126IO_1V5
127IO_3V3
128IO_1V5
129GND
130IO_1V5
131IO_1V5
132IO_1V5
133IO_1V5
134IO_1V5
135IO_1V5
136IO_3V3
Edge PadVoltage
137IO_1V5
138IO_3V3
139IO_3V3
140IO_3V3
141IO_3V3
142IO_3V3
143IO_1V5
144IO_3V3
145IO_1V5
146IO_3V3
147IO_1V5
148IO_3V3
149IO_1V5
150IO_3V3
151IO_1V5
152IO_3V3
153IO_1V5
154IO_3V3
155IO_1V5
156IO_3V3
157IO_1V5
158IO_3V3
159IO_1V5
160IO_3V3
161IO_1V5
162IO_3V3
163NC
164IO_3V3
165NC
166IO_3V3
167NC
168NC
169NC
170NC
Edge PadVoltage
171NC
172NC
173NC
174NC
175GND
176NC
177GND
178NC
179NC
180NC
181NC
182NC
183NC
184GND
185GND
186GND
187GND
188VCC_1V3
189VCC_2V5
190VCC_1V3
191VCC_2V5
192VCC_1V3
193VCC_2V5
194VCC_1V3
195VCC_2V5
196NC
197VCC_2V5
198NC
199VCC_2V5
200GND
201NC
202GND
203GND
204GND