H.265 4K Encoder IP core
2EC-VA-H265-10B-30-4K-IP-ZL
Description
System-On-Chip Technologies' IP cores are known for ultra-low latency, low power-consumption, and precise video quality. Customers from over 20 countries rely on SOC high-performance IP cores for reliable, high-efficiency all-hardware MPEG video coding.
Specifications
| Compression Standard : | H.265/HEVC |
|---|---|
| Codec Function : | Encoding |
| Channels : | Two |
| Max. Resolution : | Up to 4K/UHD (3840x2160) |
| Max. Framerate : | Up to 30 FPS (30/29.97, 25/24.97, 24/23.98...) |
| Audio Capability : | AAC, MPEG2-LayerII Audio |
| Precision : | 10 bits per channel |
| Latency : | Zero Latency (0.25ms) |
| Architecture : | All-hardware-logic |
Files & Documentation
Learn More
Standard:
H.265
H.265/HEVC is the third-generation (next-generation) MPEG Codec standard developed by MPEG.
Codec:
Encoder
An encoding system receives raw video from a camera/player/PC and transmit Transport/Program/Elementary Stream(s) to a destination over UDP.
Channels:
Two
Supports encoding/decoding of up to 2 input/output channels at the specified resolution and frame-rate.
Resolution:
4K
4K Ultra-HD (UHD) Codecs are optimized to process video frames up to 3840 pixels wide and 2160 pixels high. 4K is equivalent to four times the pixels of FHD. Resolutions exceeding these limits may be prepared by special request.
FPS:
30fps
30fps supports frame-rates up to 30fps including FPS/1.001 (29.97, 24.97, 23.98, etc.)
Audio:
Video/Audio
Video-Audio Codecs process both video and audio data. Audio data is encoded/decoded as AAC or MPEG2-LayerII.
Precision:
10 bits
10-bit extended color precision adds 4 times more color coding precision compared to 8-bit.
Latency:
Zero Latency
The zero-latency line produce the minimum latency. ZL cores encode/decode data at approximately 0.25ms at 60fps. An end-to-end latency of less than 1/4 of a frame is achieable under controlled conditions. 1-1.5 frame latency is achievable under normal conditions.
Architecture:
All-hardware-logic
SOC Technologies' IP cores are based on single-clock driven, all-hardware-logic architecture with no processors, software, or DSP processors.