H.265 4K Decoder IP core
DC-VA-H265-10B-60-4K-IP-ZL
Description
System-On-Chip Technologies' IP cores are known for ultra-low latency, low power-consumption, and precise video quality. Customers from over 20 countries rely on SOC high-performance IP cores for reliable, high-efficiency all-hardware MPEG video coding.
Specifications
| Compression Standard : | H.265/HEVC |
|---|---|
| Codec Function : | Decoding |
| Channels : | One |
| Max. Resolution : | Up to 4K/UHD (3840x2160) |
| Max. Framerate : | Up to 60 FPS (60/59.94, 50/49.95, ...) |
| Audio Capability : | AAC, MPEG2-LayerII Audio |
| Precision : | 10 bits per channel |
| Latency : | Zero Latency (0.25ms) |
| Architecture : | All-hardware-logic |
Files & Documentation
Learn More
Standard:
H.265
H.265/HEVC is the third-generation (next-generation) MPEG Codec standard developed by MPEG.
Codec:
Decoder
A decoding system receives compressed Transport/Elementary/Program Stream(s) from a source over UDP, and decode it into raw HDMI/SDI video for a display.
Channels:
One
Supports encoding/decoding of up to 1 input/output channel at the specified resolution and frame-rate.
Resolution:
4K
4K Ultra-HD (UHD) Codecs are optimized to process video frames up to 3840 pixels wide and 2160 pixels high. 4K is equivalent to four times the pixels of FHD. Resolutions exceeding these limits may be prepared by special request.
FPS:
60fps
60fps supports frame-rates up to 60fps including FPS/1.001 (59.95, 49.95, etc.)
Audio:
Video/Audio
Video-Audio Codecs process both video and audio data. Audio data is encoded/decoded as AAC or MPEG2-LayerII.
Precision:
10 bits
10-bit extended color precision adds 4 times more color coding precision compared to 8-bit.
Latency:
Zero Latency
The zero-latency line produce the minimum latency. ZL cores encode/decode data at approximately 0.25ms at 60fps. An end-to-end latency of less than 1/4 of a frame is achieable under controlled conditions. 1-1.5 frame latency is achievable under normal conditions.
Architecture:
All-hardware-logic
SOC Technologies' IP cores are based on single-clock driven, all-hardware-logic architecture with no processors, software, or DSP processors.